1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which can be miniaturized.
2. Related Art
With high integration of semiconductor devices, miniaturization of an insulated gate field effect transistor (hereinafter referred to as MIS transistor) is required to restrain increase of chip size.
There has been proposed a MIS transistor with extension structure which has a low concentration impurity region and a highly doped high concentration impurity region adjacent to the low concentration impurity region so that breakdown or degradation of property does not occur when a high voltage is applied between a source and a drain of the MIS transistor.
Conventionally, the extension structure has been formed by ion implantation of impurities using a gate electrode or a sidewall formed on a side face of the gate electrode as a mask (see, for example; Japanese Patent Laid-Open Publication No. 101238/1991, page 3, FIG. 1).
The above document discloses that a silicon nitride film and a silicon oxide film are sequentially deposited so as to overlap the whole surface of the gate electrode, and then the silicon oxide is remained only on the sidewalls of the gate electrode by performing an anisotropic etching of the silicon oxide film. Since the silicon nitride has a large etching selection ratio to a silicon substrate, the silicon nitride acts as an etch stopper during the anisotropic etching in order to prevent over-etching.
However, in the method of manufacturing the semiconductor device disclosed in the above document, low concentration impurities are introduced using the gate electrode directly as a mask. Because of this, as a gate length of the MIS transistor is shortened with miniaturization of the MIS transistor, diffusion of impurities under the gate electrode cannot be ignored.
Therefore, it is necessary to introduce low concentration impurities by using a sidewall formed on the side face of the gate electrode as the mask. However, in a conventional method of forming the sidewall, there is a problem that, as the thickness of an insulating film on the side face of the gate electrode becomes thinner (i.e. 10 nm or less) with the miniaturized MIS transistor, it is difficult to obtain a desirable sidewall shape.
That is, when the silicon oxide film is formed as a thin insulating film and an anisotropic etching is performed by RIE method, a reaction product obtained by the etching is again deposited on the silicon oxide film according to etching conditions. Therefore, a bottom side of the silicon oxide film at the lower side of the gate electrode spreads. This results in a fluctuation of a film thickness of a final sidewall used as a mask of ion implantation.
Furthermore, as the silicon nitride film becomes thin, the silicon nitride film does not properly function as a stopper of the anisotropic etching. In accordance with conditions for etching the thin insulating film, there may be a problem in that a silicon substrate disposed at bottom side is etched, and a step is formed between the gate electrode and the silicon substrate.
Accordingly, a distance between the gate electrode and a low concentration impurity region or a high concentration impurity region fluctuates, and a desirable extension structure is not obtained, thereby fluctuating properties of the MIS transistor.